The present invention relates to an improvement of a phase-locked loop circuit, and more particularly to an improved design of a phase-locked loop circuit for improving the operating frequency range and the stability of middle/low frequency thereof, and for adjusting accurately the frequency continuously.
A conventional phase-locked loop circuit is shown in FIG. 1, in which a signal fin of some frequency is inputted into a divider 11 for being frequency divided by M to become a signal fin/M, and then inputted into a phase frequency detector 12.
The phase frequency detector 12 will be inputted with another feedback signal fr having the same frequency with fin/M. The signal fr is a modified reference signal for adjusting the phase of fin/M. If the phase of fin/M is ahead of fr, then the phase frequency detector 12 will generate an UP signal. If the phase of fin/M falls behind fr, then the phase frequency detector 12 will generate a DN signal.
The UP signal or the DN signal will be inputted into a charge pump circuit 13 for generating a corresponding voltage Vctrl to be inputted into a low pass filter 14.
The output Vo of the low pass filter 14 will be inputted into a voltage controlled oscillator 15 for generating an oscillating signal to be inputted into a prescaler circuit 16. After being processed by the prescaler circuit 16, an oscillating signal fo will be inputted into a divider 17 for generating a required accurate frequency.
The signal fo is also inputted into another divider 18 for being frequency divided by N to generate the signal fr, and then inputted into the phase frequency detector 12. The frequency of fr is the same as that of fin/M.
Referring to FIG. 2, the detailed circuit of the voltage-controlled oscillator 15 will be described. A voltage signal VM is inputted into the control terminals of the inverters 21, 22, 23, 24, 25 simultaneously. The inverters 21, 22, 23, 24, 25 are connected serially to form a ring, as shown in the figure. Capacitors C1, C2, C3, C4, C5 are each parallelly connected at the output terminals a, b, c, d, e of the inverters. Therefore, oscillating signals having same frequency but different phases are each generated at the output terminals a, b, c, d, e of the inverters.
Referring to FIG. 3, which shows an improvement for the circuit in FIG. 2. The improvement is that capacitors C11, C12, C13, capacitors C21, C22, C23, capacitors C31, C32, C33, capacitors C41, C42, C43, and capacitors C51, C52, C53 are connected parallelly at the output terminals a, b, c, d, e of the inverters respectively. Signals CC1, CC2 and CC2 are used to enable switches S11, S12, S13, switches S21, S22, S23, switches S31, S32, S33, switches S41, S42, S43 and switches S51, S52, S53 that are connected serially with related capacitors respectively. By selecting signals CC1, CC2 or CC3 to turn related switches on and to enable related capacitors to become conductive, the frequency of the signals at the output terminals a, b, c, d, e can be adjusted.
Although the frequency of the signals at the output terminals a, b, c, d and e in FIG. 3 can be adjusted, the adjustment cannot be continuous. Another disadvantage is that the sensitivity of the frequency to voltage is too high in middle/low frequency range, so it is hard to do the frequency adjustment accurately.
It is therefore an object of the present invention to provide an improved design of a voltage-controlled oscillator of a phase-locked loop circuit for improving the operating frequency range and the stability of middle/low frequency therefore, and for adjusting accurately the frequency continuously.
FIG. 1 shows the block diagram of a conventional phase-locked loop circuit.
FIG. 2 shows the circuit diagram of the voltage-controlled oscillator in a conventional phase-locked loop circuit.
FIG. 3 shows a prior improved circuit design of the voltage-controlled oscillator in a conventional phase-locked loop circuit.
FIG. 4 shows an improved circuit design of the voltage-controlled oscillator in a phase-locked loop circuit according to the present invention.